LOADBench: A Large Open Analog Dataset and Benchmark for Machine Learning in IC Design

TL;DR

LOADBench introduces a large open dataset and standardized benchmarks for machine learning in analog IC design, featuring over 100 operational amplifier topologies with detailed annotations, testbenches, and Pareto-optimal sizing data. It enables reproducible evaluation across six defined tasks, addressing long-standing issues of data scarcity and inconsistent benchmarking in the field.

Why It Matters

The lack of shared datasets and consistent evaluation protocols has hindered progress in analog IC design automation. LOADBench enables fair comparisons between methods, accelerates research, and supports the development of reliable ML-driven design tools.

Key Findings

• The dataset includes more than 100 opamp topologies across 1-, 2-, and 3-stage designs with structural and functional annotations.
• Each topology is accompanied by Ngspice testbenches and NSGA-II-generated Pareto-optimal and intermediate sizing-performance pairs.
• Six standardized benchmark tasks—inverse sizing, topology selection, sub-circuit classification, structural generation, Pareto-membership prediction, and multi-objective optimization—are defined with clear protocols.